1. Field of the Invention
This invention pertains to a memory access controller for use with microprocessors. The memory access controller (MAC) combines several functions into a single chip circuit design. It serves as a memory management unit (MMU) which controls access to memory and maps virtual addresses into real addresses. It also serves as a cache controller for speeding up access by the processor to the memory. The memory access controller combines these functions in such a way that they can be performed in parallel, resulting in a more economical and faster implementation of these functions.
2. Description of the Prior Art
Both memory management units and cache controllers are well known in the prior art. In the rapidly evolving state of the art, two such devices have received extensive publicity recently. These devices are the NS 16082 Memory Management Unit of National Semiconductor Corporation and the BELLMAC-32 Memory Management Unit of Western Electric Company.
The NS 16082 Memory Management Unit provides hardware support for demand paged virtual memory management. Its specific capabilities include fast dynamic address translation, protection on individual 512 byte pages and detailed status to assist an operating system in efficiently managing up to 16 megabytes of physical memory. High speed address translation is performed on the chip through a 32 entry associative cache which maintains itself in tables in memory with no software intervention. Protection violations and page faults are automatically detected by this memory management unit. This unit is available as a 48 pin dual-in-line package.
The BELLMAC-32 memory management unit performs address translation for both continuous segment and demand paging systems. It facilitates systematic memory organization for operating systems by partitioning virtual address space into manageable units of sections, segments and pages. It provides access protection. It further includes descriptor caches on the chip. There is a directly mapped, 32 entry segment descriptor cache and a two-way set associative, 64 entry page descriptor cache. To translate an address, the BELLMAC-32 memory management unit searchs its descriptor caches for relevant descriptors. If the descriptors are present, this unit checks for length violation and access permission violation. For continuous segments the translation is done by adding the segment base addresses from the cache segment descriptor to an offset from the virtual address to form the physical address. For paged segments this unit concatinates a page base address from the cached page descriptor to the page offset, from the virtual address, to form the physical address.
The memory access controller of the present invention is directed to a significantly improved performance level which is achieved by addressing some of the problems which exist even in the recent state of the art memory management units. By integrating a cache controller and a memory management unit in one circuit, the present invention can use virtual addresses to retrieve data from a cache memory. Additionally virtual input/output operations can be performed. The most significant improvement is the increase in system speed. By acting as a cache controller, access to data in caches is greatly enhanced. The memory access controller can relieve a bus of up to 80% of its load, thus allowing up to four processors to coexist on a bus. Multiprocessing is enhanced in other ways including the provision of a three level storage hierarchy. In short, the memory access controller allows a processor to run at full speed, provides a flexible scheme of relocating which can be extended into virtual memory, provides facilities for wide range of protection systems from trivial to the most complex and provides all the facilities to allow application programs to migrate from single processor systems to multiprocessor systems without change.
Even the 8 MHz Motorola 68010 poses problems for the system designer with regard to speed and memory management. In most real, modular systems, an 8 MHz 68010 with a 68451 MMU (Motorola) will need between two and four wait states when it accesses memory. This problem will only get worse when the higher speed 68010s and 68020s become available. This problem will be slightly reduced when the 256K DRAM is easily obtainable but it is clear that a 16 MHz 680x0 and 68451 will need at least four wait states when accessing memory unless that memory is not on a bus.